Loading repository data…
merledu / repository
This repository contains the verilog code files of Single Cycle RISC-V architecture
A transparent discovery signal based on current public GitHub metadata.
This score does not audit code, security, maintainers, documentation quality, or suitability. Verify the repository and its current documentation before adoption.
Selected from shared topics, language and repository description—not editorial ratings.
viduraakalanka /
This is a repository containing solutions to the problem statements given in HDL Bits website.
70/100 healthicebreaker-fpga /
This repository contains small example designs that can be used with the open source icestorm flow.
17/100 healthnxbyte /
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
alknvl /
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
71/100 healthEscapeTHU /
This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog. Code in this repo contains both C++ SGBM simulation code and PS-PL vitis-vivado project. Tutorial and the video attached thoroughly explain my designation in detail, although made in Chinese hhhhh.
62/100 healthmmdnmz /
Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functioning CNN hardware accelerator based on the Eyeriss‑V1 architecture. Designed for energy‐efficient deep learning, the design implements the row‑stationary dataflow to maximize data reuse and minimize data movement.
61/100 health