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alknvl / repository
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
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This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
Before simulation, you need specify the path to output file with network traffic dump
axis_udp/tb/udp_tb.sv:
localparam DUMP_PATH = "/home/usr/dump.txt";
After simulation, you can use tool axis2net.py to convert network traffic dump in *.pcap format. Then you can use WireShark to analyze network packets.
$ python3 axis2net.py /home/usr/dump.txt --o /home/usr/dump.pcap
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ceaj91 /
This repository contains an AXI-Stream sorting IP block written in Verilog. The design supports an AXI-Stream input and output interface, making it suitable for FPGA and ASIC-based sorting applications. Formal verification has been performed using JasperGold to ensure correctness and reliability
34/100 health