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Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
#adder#comparator#decoder#encoder#full-adder#half-adder
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Verilog Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs.
To Run & Test
There are two ways to run and simulate the projects in this repository. Either use Xilinx Vivado or an online tool called EDA Playground.
Option 1. Xilinx Vivado
- Run the Xilinx Vivado Suite with the module and testbench files within each project. More instructions can be found here.
Option 2. EDA Playground
- Login with a Google or Facebook account to save and run modules and testbenches
- Testbench + Design: SystemVerilog/Verilog
- Tools & Simulators: Icarus Verilog 0.9.7
Projects
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Half Adder: This half adder adds two 1-bit binary numbers and outputs the sum of the input and its corresponding carry.
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Full Adder: This full adder takes 3-bits for the input (A, B and carry in) and outputs a 2-bit Sum and its corresponding Carry Out. The Sum will be the lowest value output and the Carry Out is the highest value output as well as where other full adders could be joined together.
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Four Bit Ripple Adder: This 4-bit adder takes advantage of the full adder module by taking four full adders and linking them together to add 2 four bit inputs. In the 4-bit adder, the first carry bit is set to zero because there is no initial carry bit as an input.
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Four Bit Look Ahead Adder: This 4-bit look ahead adder is an improved implementation of a 4-bit ripple adder by eliminating the propagation delay found in the 4-bit ripple adder. For each output, this implementation computes each previous carry simultaneously instead of waiting for the previous adder module to yield a carry. In this adder, the first carry bit is set to zero and simplifies the logic because there is no initial carry bit as the input. While this implementation uses more gates and more complex logic to accomplish the same task as the ripple adder, this implementation would add two 4-bit numbers much faster than the 4-bit ripple adder.
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3-bit Comparator: This 3-bit comparator requires two 3-bit inputs and outputs whether the first input is greater than / less than / or equal to the second input. In practice, the 3-bit comparator would compare two numbers and output the relation between them. To verify this module, the binary input bits were converted into their decimal representation and compared mathematically, example: inputs of 010 and 010 represent, 2 and 2, which the module would output 001 for the outputs: GT, LT, and EQ, respectively.
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4-16 Decoder: This 4-to-16 decoder takes one 4-bit input and outputs a 16-bit representation of the input. This module uses the concept of one-hot decoding where each output would have one output that would correspond to the input. An application for this decoder would be to convert a 4-bit binary value to its hexadecimal representation. To verify this module, the binary bits of the input is converted into their decimal representation and compared to the output’s decimal representation to see if they match.
License
All source code in Verilog-Projects are released under the MIT license. See LICENSE for details.