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gfto / repository
biTStream is a set of C headers allowing a simpler access to binary structures such as specified by MPEG, DVB, IETF, etc. This repository is mirror of official repo at git://git.videolan.org/bitstream.git and my personal development tree.
biTStream is a set of C headers allowing a simpler access to binary structures such as specified by MPEG, DVB, IETF, etc.
libdvbpsi converts binary structures to C structures. Lists are implemented with chained lists of C structures.
biTStream is lower level, and more efficient: fewer memory allocations, fewer memory copies. It also features a better separation between layers and specifications.
A lot of MPEG and DVB tables and descriptors are not implemented yet, or are incomplete. Patches are very welcome.
Though biTStream is originally targeted at video applications in general and MPEG-2 transport stream in particular, the same principle can be followed with other binary data types, and patches are welcome here too. Just try to follow a coherent directory naming.
My coding style is Linux kernel + Hungarian conventions. Really, I do not care about the coding style of new files; do (WTF) you want. However, for existing files, please try to follow the original conventions.
biTStream is released under the MIT license because since it is a direct application of standards, there is no added value. The MIT license doesn't require you to contribute back your changes, and you can use biTStream in proprietary applications. However, if you add new structures, or fix bugs in current structures, you'd be very nice to contribute them (again, there is no point in concealing this). Thanks.
To see what is unsupported look in the TODO file.
To see biTSream in action look in examples directory.
Selected from shared topics, language and repository description—not editorial ratings.
Fraunhofer-IIS /
The iec61937-13 project is a C based implementation of the IEC 61937-13:2018 standard and covers the encapsulation of MPEG-H bitstream in IEC data bursts
bodhisattwa-chakraborty /
This program generates a concave hull (an envelope surrounding the point data set) around any two-dimensional data set. The algorithm uses K-nearest neighbour approach to compute the concave hull. This approach is based on the paper "CONCAVE HULL: A K-NEAREST NEIGHBOURS APPROACH FOR THE COMPUTATION OF THE REGION OCCUPIED BY A SET OF POINTS," GRAPP 2007 - International Conference on Computer Graphics Theory and Applications, pp. 61-68, 2007, by Adriano Moreira and Maribel Yasmina Santos. (http://repositorium.sdum.uminho.pt/bitstream/1822/6429/1/ConcaveHull_ACM_MYS.pdf). The convex hull is being computed using Matlab inbuilt 'convhulln' function. A comparative analysis based on the area covered by the convex and concave hull and the run time for each method is also presented. The 'degree of concaveness' is calculated based on the difference between the convex hull and concave hull.
sukrutkelkar /
Demonstrated acceleration achieved due to parallel computing on FPGA is much higher than that achieved on a Multicore CPU. Matrix Multiplication of two 1000x1000 matrices (A and B) was used for demonstration. This includes computation of 1 million data points. A Kernel was developed that would work on one row of Matrix and one column of matrix B at a time. OpenCL allows to replicate these kernels, generating parallel design blocks on the FPGA. Buffers were created on the FPGA which will hold the data of the two matrices. Each Kernel will read from a specific location, perform its operation and store the result in another buffer eventually to form Matrix C which is the resultant matrix. Use of OpenCL added an abstraction layer which would convert the code written in C to a netlist further to form a bitstream to be synthesized on the FPGA.
haringd /
This tutorial guides you through the design flow using Xilinx Vivado software to create a simple digital circuit using Verilog. A typical design flow consists of creating model(s), creating user constraint file(s), creating a Vivado project, importing the created models, assigning created constraint file(s), optionally running behavioral simulation, synthesizing the design, implementing the design, generating the bitstream, and finally verifying the functionality in the hardware by downloading the generated bitstream file. You will go through the typical design flow targeting the ZYNQ-7000 based PYNQ board. The typical design is shown below.
AEjonanonymous /
VES-369 is a Tesla-inspired 3-6-9 mapping protocol for deterministic wire-speed compression and bit-true parity across JS, C++, and Silicon implementations.
jpbaltazar /
This project is a compiler that turns a file of PCRE expressions and turns it into a C++ header and source files that describe an engine to match the text to the regular expressions. This engine is then put through a HLS tool (Vitis HLS) to get an FPGA bitstream of the engine.