sukrutkelkar / repository

OpenCL-Based-Hardware-Acceleration

Demonstrated acceleration achieved due to parallel computing on FPGA is much higher than that achieved on a Multicore CPU. Matrix Multiplication of two 1000x1000 matrices (A and B) was used for demonstration. This includes computation of 1 million data points. A Kernel was developed that would work on one row of Matrix and one column of matrix B at a time. OpenCL allows to replicate these kernels, generating parallel design blocks on the FPGA. Buffers were created on the FPGA which will hold the data of the two matrices. Each Kernel will read from a specific location, perform its operation and store the result in another buffer eventually to form Matrix C which is the resultant matrix. Use of OpenCL added an abstraction layer which would convert the code written in C to a netlist further to form a bitstream to be synthesized on the FPGA.