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EGR680_FPGA_Counter_Lab1

This tutorial guides you through the design flow using Xilinx Vivado software to create a simple digital circuit using Verilog. A typical design flow consists of creating model(s), creating user constraint file(s), creating a Vivado project, importing the created models, assigning created constraint file(s), optionally running behavioral simulation, synthesizing the design, implementing the design, generating the bitstream, and finally verifying the functionality in the hardware by downloading the generated bitstream file. You will go through the typical design flow targeting the ZYNQ-7000 based PYNQ board. The typical design is shown below.