circuitvalley /
USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
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FHDO-ICLAB / repository
This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from Cologne Chip
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This repository contains the schematic and layout for a prototype evaluation board for the Cologne Chip Gatemate FPGA and the Verilog source of a MIPI-CSI-2-HDMI-bridge. The evaluation board is designed to enable the use of a Raspberry Pi Camera V2 for receiving and an HDMI port for transmitting video data, however it may be useful to make some adjustments to the design.
The Verilog design is a demonstrator system consisting of a MIPI-CSI-2 capable receiver, a rudimentary framebuffer and a DVI output that can be used to drive HDMI displays, as HDMI is backwards-compatible with DVI. Note that the CSI-2 receiver is a minimalist implementation design to meet the requirements of the Raspberry Pi Camera V2 and in the current version only supports one data type. Support for other data types can be implemented with just a few changes to the code.
More information can be found in the Master's Thesis about this project at: https://doi.org/10.26205/opus-3922
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circuitvalley /
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
78/100 healthnxbyte /
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
76/100 healthJohnlon /
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
alknvl /
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
71/100 healthEscapeTHU /
This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog. Code in this repo contains both C++ SGBM simulation code and PS-PL vitis-vivado project. Tutorial and the video attached thoroughly explain my designation in detail, although made in Chinese hhhhh.
62/100 healthBoChen-Ye /
This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
75/100 health