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Verification of Advanced Encryption Standard (AES-128) Using the Universal Verification Methodology (UVM).
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This project involves the verification of an AES-128 Encryption Engine using the Universal Verification Methodology (UVM). The AES-128 encryption engine is a hardware block that takes in a 128-bit plaintext and a 128-bit cipher key to produce a 128-bit encrypted output (ciphertext).
The block diagram of the AES-128 Encryption Engine is as follows:
The UVM testbench is composed of several components to facilitate the verification process. The key components include:
The stimulus generation is handled by the UVM sequence, which drives different sequences of data, such as:
Functional coverage is collected to ensure that all parts of the AES algorithm are exercised. The coverage model includes:
valid_in, reset_n and clock cycles during operation.plain_text and cipher_key.Selected from shared topics, language and repository description—not editorial ratings.
This project implements a complete UVM-based verification environment for an AES-128 encryption/decryption RTL design written in Verilog. The goal is to verify functional correctness of the AES core using UVM testbench and Python golden reference model
42/100 healthdata_outvalid_outSystemVerilog assertions (SVA) are used to validate the protocol and timing of the AES-128 engine. Key assertions include:
valid_out is asserted.Ensure that you have the following tools installed:
Run the tests using the following command:
do run.do