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Nada44yehia / repository
This project implements a complete UVM-based verification environment for an AES-128 encryption/decryption RTL design written in Verilog. The goal is to verify functional correctness of the AES core using UVM testbench and Python golden reference model
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Johnlon /
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
81/100 healthalknvl /
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
71/100 healthlllbbbyyy /
This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
EscapeTHU /
This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog. Code in this repo contains both C++ SGBM simulation code and PS-PL vitis-vivado project. Tutorial and the video attached thoroughly explain my designation in detail, although made in Chinese hhhhh.
62/100 healthlerogo /
实现了5段流水的CPU This project is verilog that implements 5-stage-pipeline-cpu
11/100 healthantonson-j1 /
This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog and synthesized using Yosys Open Synthesis Suite. The optimized designs are then compared with a base-line C implementation in software. Hash functions are used to securely store passwords, to quickly store and retrive data, and also to check if a file/message is corrupted.
49/100 health