Edge AI CNN Inference Engine on FPGA

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Hardware implementation of a lightweight Convolutional Neural Network (CNN) inference engine using Verilog HDL and synthesized using Xilinx Vivado 2026.1.

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CNN Hardware Architecture

The architecture implements a complete CNN inference pipeline entirely in RTL hardware. Image data flows through convolution, activation, pooling, flattening, dense classification, and ArgMax prediction, demonstrating an FPGA-oriented Edge AI accelerator.

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📖 Project Overview

This project presents the RTL implementation of a lightweight CNN inference engine designed for FPGA-based Edge AI applications.

Unlike software-based neural networks, every processing stage has been implemented as dedicated hardware modules in Verilog HDL, allowing the complete inference pipeline to be synthesized for FPGA deployment.

The project demonstrates modular RTL design, hardware acceleration concepts, memory-based parameter storage, and complete FPGA synthesis using Xilinx Vivado.

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✨ Features

• ✅ 3×3 Convolution Engine
• ✅ MAC-Based Convolution
• ✅ Feature Map Generator
• ✅ ReLU Activation
• ✅ 2×2 Max Pooling
• ✅ Flatten Layer
• ✅ Fully Connected Dense Layer
• ✅ ArgMax Classifier
• ✅ Parameterized RTL Design
• ✅ Weight Memory
• ✅ Kernel Memory
• ✅ Multi-Kernel CNN Support
• ✅ Parallel Processing
• ✅ FPGA Ready RTL
• ✅ Vivado Synthesis

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⚙ CNN Processing Pipeline

Input Image (5×5)

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3×3 Convolution

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Feature Maps

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ReLU Activation

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2×2 Max Pooling

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Flatten Layer

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Dense Layer

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ArgMax

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Predicted Class

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📂 Project Structure

Edge-AI-CNN-Inference-Engine-on-FPGA

├── rtl/
├── testbench/
├── constraints/
├── memory/
├── docs/
├── vivado/
├── README.md
└── LICENSE

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RTL Schematic

The RTL schematic illustrates the hierarchical implementation of the CNN accelerator in hardware.

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Synthesized Schematic

The synthesized netlist generated by Xilinx Vivado demonstrates successful hardware mapping of the RTL design.

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📊 FPGA Resource Utilization

The design occupies only a small percentage of available FPGA resources while maintaining a modular architecture.

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⏱ Timing Report

Timing analysis confirms successful synthesis. The design is fully synthesizable and ready for further FPGA implementation.

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📈 Project Statistics

Category	Details
Language	Verilog HDL
Development Tool	Xilinx Vivado 2026.1
Design Style	RTL
CNN Layers	Convolution → ReLU → Pool → Flatten → Dense → ArgMax
Memory Support	Weight Memory + Kernel Memory
FPGA Compatible	✅
Synthesis	✅ Successful
GitHub	Public Repository

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Verification Status

Module	Status
MAC Unit	✅
Conv3×3	✅
Feature Map Generator	✅
ReLU	✅
Max Pooling	✅
Flatten	✅
Dense Layer	✅
ArgMax	✅
Integrated CNN	✅
RTL Simulation	✅
RTL Synthesis	✅

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🔮 Future Improvements

• Multi-channel RGB image support
• Multiple convolution layers
• Batch Normalization
• Softmax Layer
• AXI4 Interface
• BRAM Image Storage
• FPGA Board Deployment
• Real-Time Edge AI Applications

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🛠 Tools & Technologies

• Verilog HDL
• Xilinx Vivado 2026.1
• FPGA RTL Design
• Digital Logic Design
• Git
• GitHub

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Author

Abhay Nagure

Electronics & Communication Engineering Student

Interested in:

• FPGA Design
• RTL Design
• Digital VLSI
• Embedded Systems
• Edge AI

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⭐ If you found this project useful, consider giving it a star!

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📄 License

This project is licensed under the MIT License.