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tatan432 / repository
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
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The part of work is related to 128-bit AES encryption algorithm RTL design. There are three parts to the design-
RTL is written in verilog, where as the testbench is written in system verilog.
The simulation environment where it is tested is DC compiler. In every part (SISO/MIMO/N-CHANNEL), there is a VCS folder. Type command: 'make all' to run the simulation. The Simulation takes the data from the ref folder. Ref folder keeps the golden data for each round as well.
Few points to be noted. The constraint in the syntheis is in the unit of ns for time and fF for capacitance (as governed by our library). To run synthesis:
To View the Design:
To View the waveform:
The test bench aes_sbox.v and matrix_mult.v is written by Saurabh Jain(User: @srbhjn459)
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yashas-cmd-spec /
AES-128 Encryption Accelerator implemented in Verilog HDL on the ZedBoard (Zynq-7000 FPGA) using AMD Vivado 2025.1. Features hardware-based encryption, RTL design, simulation, synthesis, implementation, and bitstream generation for secure, high-performance cryptographic applications.
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