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Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
#analog-design#cadence-virtuoso#matlab#pll#veriloga
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Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
[1] PLL System Design
- PLL block diagram:
- Typical CP PLL system:
- System Parameters:
- System Stability:
- Open-Loop & Closed-Loop Parameters:
- VerilogA System Simulation:
[2] PLL Circuit Design
A) PFD:
B) Charge Pump:
C) Loop Filter:
1- With LC VCO:
2- With Ring VCO:
