Neural Networks on Silicon

Fengbin Tu is an Assistant Professor and the Associate Director of the Institute of Integrated Circuits and Systems at The Hong Kong University of Science and Technology, NSFC Excellent Young Scientist, and a core faculty member of the AI Chip Center for Emerging Smart Systems (ACCESS) under InnoHK. For more informantion about Dr. Tu, please refer to his homepage. Dr. Tu's main research interest is AI chip and system. This is an exciting field where fresh ideas come out every day, so he's collecting works on related topics. Welcome to join!

Table of Contents

• My Contributions
• Conference Papers
  • 2014: ASPLOS, MICRO
  • 2015: ISCA, ASPLOS, FPGA, DAC
  • 2016: ISSCC, ISCA, MICRO, HPCA, DAC, FPGA, ICCAD, DATE, ASPDAC, VLSI, FPL
  • 2017: ISSCC, ISCA, MICRO, HPCA, ASPLOS, DAC, FPGA, ICCAD, DATE, VLSI, FCCM, HotChips
  • 2018: ISSCC, ISCA, MICRO, HPCA, ASPLOS, DAC, FPGA, ICCAD, DATE, ASPDAC, VLSI, HotChips
  • 2019: ISSCC, ISCA, MICRO, HPCA, ASPLOS, DAC, FPGA, ICCAD, ASPDAC, VLSI, HotChips, ASSCC
  • 2020: ISSCC, ISCA, MICRO, HPCA, ASPLOS, DAC, FPGA, ICCAD, VLSI, HotChips
  • 2021: ISSCC, ISCA, MICRO, HPCA, ASPLOS, DAC, ICCAD, VLSI, HotChips
  • 2022: ISSCC, ISCA, MICRO, HPCA, ASPLOS, HotChips
  • 2023: ISSCC, ISCA, MICRO, HPCA, ASPLOS, HotChips
  • 2024: ISSCC, ISCA, MICRO, HPCA, ASPLOS, HotChips
  • 2025: ISSCC, ISCA, MICRO, HPCA, ASPLOS, HotChips
  • 2026: ISSCC, HPCA

My Contributions

My main research interest is AI chip and architecture. For more informantion about me and my research, you can go to my homepage.

Conference Papers

This is a collection of AI chip-related conference papers that interest me.

2014 ASPLOS

• DianNao: A Small-Footprint High-Throughput Accelerator for Ubiquitous Machine-Learning. (CAS, Inria)

2014 MICRO

• DaDianNao: A Machine-Learning Supercomputer. (CAS, Inria, Inner Mongolia University)

2015 ISCA

• ShiDianNao: Shifting Vision Processing Closer to the Sensor. (CAS, EPFL, Inria)

2015 ASPLOS

• PuDianNao: A Polyvalent Machine Learning Accelerator. (CAS, USTC, Inria)

2015 FPGA

• Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. (Peking University, UCLA)

2015 DAC

• Reno: A Highly-Efficient Reconfigurable Neuromorphic Computing Accelerator Design. (Universtiy of Pittsburgh, Tsinghua University, San Francisco State University, Air Force Research Laboratory, University of Massachusetts.)
• Scalable Effort Classifiers for Energy Efficient Machine Learning. (Purdue University, Microsoft Research)
• Design Methodology for Operating in Near-Threshold Computing (NTC) Region. (AMD)
• Opportunistic Turbo Execution in NTC: Exploiting the Paradigm Shift in Performance Bottlenecks. (Utah State University)

2016 DAC

• DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family. (Chinese Academy of Sciences)
  • Hardware generator: Basic buliding blocks for neural networks, and address generation unit (RTL).
  • Compiler: Dynamic control flow (configurations for different models), and data layout in memory.
  • Simply report their framework and describe some stages.
• C-Brain: A Deep Learning Accelerator that Tames the Diversity of CNNs through Adaptive Data-Level Parallelization. (Chinese Academy of Sciences)
• Simplifying Deep Neural Networks for Neuromorphic Architectures. (Incheon National University)
• Dynamic Energy-Accuracy Trade-off Using Stochastic Computing in Deep Neural Networks. (Samsung, Seoul National University, Ulsan National Institute of Science and Technology)
• Optimal Design of JPEG Hardware under the Approximate Computing Paradigm. (University of Minnesota, TAMU)
• Perform-ML: Performance Optimized Machine Learning by Platform and Content Aware Customization. (Rice University, UCSD)
• Low-Power Approximate Convolution Computing Unit with Domain-Wall Motion Based “Spin-Memristor” for Image Processing Applications. (Purdue University)
• Cross-Layer Approximations for Neuromorphic Computing: From Devices to Circuits and Systems. (Purdue University)
• Switched by Input: Power Efficient Structure for RRAM-based Convolutional Neural Network. (Tsinghua University)
• A 2.2 GHz SRAM with High Temperature Variation Immunity for Deep Learning Application under 28nm. (UCLA, Bell Labs)

2016 ISSCC

• A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems. (KAIST)
• Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. (MIT, NVIDIA)
• A 126.1mW Real-Time Natural UI/UX Processor with Embedded Deep Learning Core for Low-Power Smart Glasses Systems. (KAIST)
• A 502GOPS and 0.984mW Dual-Mode ADAS SoC with RNN-FIS Engine for Intention Prediction in Automotive Black-Box System. (KAIST)
• A 0.55V 1.1mW Artificial-Intelligence Processor with PVT Compensation for Micro Robots. (KAIST)
• A 4Gpixel/s 8/10b H.265/HEVC Video Decoder Chip for 8K Ultra HD Applications. (Waseda University)

2016 ISCA

• Cnvlutin: Ineffectual-Neuron-Free Deep Convolutional Neural Network Computing. (University of Toronto, University of British Columbia)
• EIE: Efficient Inference Engine on Compressed Deep Neural Network. (Stanford University, Tsinghua University)
• Minerva: Enabling Low-Power, High-Accuracy Deep Neural Network Accelerators. (Harvard University)
• Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. (MIT, NVIDIA)
  • Present an energy analysis framework.
  • Propose an energy-efficienct dataflow called Row Stationary, which considers three levels of reuse.
• Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory. (Georgia Institute of Technology, SRI International)
  • Propose an architecture integrated in 3D DRAM, with a mesh-like NOC in the logic layer.
  • Detailedly describe the data movements in the NOC.
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. (University of Utah, HP Labs)
  • An advance over ISAAC has been published in "Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration" (IEEE Micro).
• A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory. (UCSB, HP Labs, NVIDIA, Tsinghua University)
• RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision. (Rice University)
• Cambricon: An Instruction Set Architecture for Neural Networks. (Chinese Academy of Sciences, UCSB)

2016 DATE

• The Neuro Vector Engine: Flexibility to Improve Convolutional Network Efficiency for Wearable Vision. (Eindhoven University of Technology, Soochow University, TU Berlin)
  • Propose an SIMD accelerator for CNN.
• Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array. (UNIST, Seoul National University)
  • The compute tile is organized on 3 dimensions: Tm, Tr, Tc.
• NEURODSP: A Multi-Purpose Energy-Optimized Accelerator for Neural Networks. (CEA LIST)
• MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. (Tsinghua University, UCSB, Arizona State University)
• Accelerated Artificial Neural Networks on FPGA for Fault Detection in Automotive Systems. (Nanyang Technological University, University of Warwick)
• Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks. (Purdue University)

2016 FPGA

• Going Deeper with Embedded FPGA Platform for Convolutional Neural Network. [Slides][Demo] (Tsinghua University, MSRA)
  • The first work I see, which runs the entire flow of CNN, including both CONV and FC layers.
  • Point out that CONV layers are computational-centric, while FC layrers are memory-centric.
  • The FPGA runs VGG16-SVD without reconfiguring its resources, but the convolver can only support k=3.
  • Dynamic-precision data quantization is creative, but not implemented on hardware.
• Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. [Slides] (Arizona State Univ, ARM)
  • Spatially allocate FPGA's resources to CONV/POOL/NORM/FC layers.

2016 ASPDAC

• Design Space Exploration of FPGA-Based Deep Convolutional Neural Networks. (UC Davis)
• LRADNN: High-Throughput and Energy-Efficient Deep Neural Network Accelerator using Low Rank Approximation. (Hong Kong University of Science and Technology, Shanghai Jiao Tong University)
• Efficient Embedded Learning for IoT Devices. (Purdue University)
• ACR: Enabling Computation Reuse for Approximate Computing. (Chinese Academy of Sciences)

2016 VLSI

• A 0.3‐2.6 TOPS/W Precision‐Scalable Processor for Real‐Time Large‐Scale ConvNets. (KU Leuven)
  • Use dynamic precision for different CONV layers, and scales down the MAC array's supply voltage at lower precision.
  • Prevent memory fetches and MAC operations based on the ReLU sparsity.
• A 1.40mm2 141mW 898GOPS Sparse Neuromorphic Processor in 40nm CMOS. (University of Michigan)
• A 58.6mW Real-Time Programmable Object Detector with Multi-Scale Multi-Object Support Using Deformable Parts Model on 1920x1080 Video at 30fps. (MIT)
• A Machine-learning Classifier Implemented in a Standard 6T SRAM Array. (Princeton)

2016 ICCAD

• Efficient Memory Compression in Deep Neural Networks Using Coarse-Grain Sparsification for Speech Applications. (Arizona State University)
• Memsqueezer: Re-architecting the On-chip memory Sub-system of Deep Learning Accelerator for Embedded Devices. (Chinese Academy of Sciences)
• Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. (Peking University, UCLA, Falcon)
  • Propose a uniformed convolutional matrix-multiplication representation for accelerating CONV and FC layers on FPGA.
  • Propose a weight-major convolutional mapping method for FC layers, which has good data reuse, DRAM access burst length and effective bandwidth.
• **BoostNoC: Power Efficient Network-on-Chip Architecture for Near Thre