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Buck008 / repository
You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.
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You can run it on pynq z1 (or any other Zynq device, since the systolic array is parameterized). The repository contains the relevant Verilog code, Vivado configuration and C/Python code for sdk/PYNQ testing. The size of the systolic array can be changed, now it is 16X16. In the future, I might add some nonlinear hardware acceleration operators (for accelerating ViT, it's a kind of neural network based on Transformer), such as those that compute Softmax, Gelu and LayerNorm functions. I am still working on to improve the accuracy and performance of this part.
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deaneeth /
A TPU you can watch run - real SystemVerilog systolic array, compiled to WASM, visualized live in your browser.
75/100 healthMrYanYe /
This is a small utility that batch converts .v files into .txt files, making it easier to feed them into LLMs that don’t support .v format. You can either run the Python script or simply download the .exe file and double‑click to run it. For more details, please refer to the README file. 这是一个批量把.v文件转换为.txt文件的小工具
34/100 healthNibiruFT /
Verilog implementation of a fully functional single-cycle MIPS CPU. The CPU will be able to run at least 10 assembly instructions. You can then program it in assembly or even C.