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AsgharAZ / repository
Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.
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This repository contains the code and documentation for a digital system design project implemented using MATLAB and Verilog. The project focuses on designing and implementing a FIR (Finite Impulse Response) Low Pass Filter (LPF) within the context of a Digital Signal Synthesizer (DDS).
The project involves the following components:
System Architecture: The architecture of the digital system, including the data path, control path, and top-level system design.
Filter Design in MATLAB: Designing a FIR LPF using MATLAB's Filter Designer tool, specifying frequency requirements and obtaining filter coefficients.
Filter Implementation in Verilog: Implementing the FIR LPF in Verilog, integrating it into the larger DDS system architecture.
Verification and Simulation: Validating the Verilog implementation through simulation and comparing results with MATLAB's ideal plots.
To reproduce the results or run simulations:
This project is licensed under the GNU License.